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| FUJITSU SEMICONDUCTOR DATA SHEET DS07-12535-2E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89850R Series MB89855R/P857/W857 s DESCRIPTION The MB89850R series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers contain a variety of peripheral functions such as a timer unit, PWM timers, a UART, a serial interface, a 10-bit A/D converter, and an external interrupt. The MB89850R series is applicable to a wide range of applications from consumer products to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller. s FEATURES * Various package options SDIP package (64 pins)/QFP package (64 pins) * High-speed processing at low voltage Minimum execution time: 0.4 s/3.5 V, 0.8 s/2.7 V (Continued) s PACKAGE 64-pin Plastic SH-DIP 64-pin Plastic QFP 64-pin Ceramic SH-DIP 64-pin Ceramic QFP (DIP-64P-M01) (FPT-64P-M06) (DIP-64C-A06) (FPT-64C-A02) (DIP-64P-M01) (FPT-64P-M06) (DIP-64C-A06) (FPT-64C-A02) MB89850R Series (Continued) * F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. * 8-bit PWM timers: 2 channels Also usable as a reload timer * UART Full-duplex double buffer Synchronous and asynchronous data transfer * 8-bit serial I/O Switchable transfer direction allows communication with various equipment. * 10-bit A/D converter Conversion time: 13.2 s Activation by an external input or a timer unit capable * External interrupt: 4 channels Four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). * Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) * Bus interface functions Including hold and ready functions * Timer unit Outputs non-overlap three-phase waveforms to control an AC inverter motor. Also usable as a PWM timer (4 channels) 2 MB89850R Series s PRODUCT LINEUP Part number Parameter MB89855R Mass production products (mask ROM products) 16 K x 8 bits (internal mask ROM) 512 x 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: Input ports: Output ports (N-ch open drain): Output ports (CMOS): I/O ports (CMOS): Total: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 s/10 MHz 3.6 s/10 MHz MB89P857 MB89W857 One-time PROM pruducts/EPROM products, also used for evaluation 32 K x 8 bits (internal PROM, programming with general-purpose EPROM programmer) 1 K x 8 bits Classification ROM size RAM size CPU functions Ports 5 (All also serve as peripherals) 8 (All also serve as peripherals) 8 (All also serve as bus control pins) 32 (All also serve as bus pins or peripherals) 53 Timer unit 10-bit up/down count timer x 1 Compare registers with buffer x 4 Compare timer unit clear register with buffer x 1 Zero detection pin control 4 output channels Non-overlap three-phase waveform output Independent three-phase dead-time timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 s to 25.6 s) 8-bit resolution PWM operation (conversion cycle: 102 s to 6.528 ms) 8-bit PWM timer 1, 8-bit PWM timer 2 UART 8-bit serial I/O 8 bits Clock synchronous/asynchronous data transfer capable 8 bits LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 s, 3.2 s, 12.8 s) 10-bit resolution x 8 channels A/D conversion time: 13.2 s Continous activation by a compare channel 0 in timer unit or an external activation capable 10-bit A/D converter External interrupt 4 independent channels (edge selection, interrupt vector, source flag) Rising edge/falling edge selectability. Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) Standby modes Process Operating voltage* 2.7 V to 6.0 V Sleep mode, stop mode CMOS 2.7 V to 5.5 V * : Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") 3 MB89850R Series s PACKAGE AND CORRESPONDING PRODUCTS Package DIP-64P-M01 DIP-64C-A06 FPT-64P-M06 FPT-64C-A02 : Available x x : Not available x x x x MB89855R MB89P857 MB89W857 x Note: For more information about each package, see section "s Package Dimensions." s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the OTPROM (one-time PROM) products (also used for evaluation), verify its differences from the product that will actually be used. Take particular care on the following point: * The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption When operated at low speed, the product with an OTPROM or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. 3. Mask Options In the MB89P857/W857, no option can be set. Before using options check section "s Mask Options." Take particular care on the following point: * A pull-up resistor can be set for P00 to P07, P10 to P17 and P20 to P27 only at single-chip mode. 4 MB89850R Series s PIN ASSIGNMENT (Top view) P31/SO1 P30/SCK1 P47/TRGI P46/Z P45/Y P44/X P43/RTO3/W P42/RTO2/V P41/RTO1/U P40/RTO0 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P64/DTTI P63/INT3/ADST P62/INT2 P61/INT1 P60/INT0 RST MOD0 MOD1 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (DIP-64P-M01) (DIP-64C-A06) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC P32/SI1 P33/SCK2 P34/SO2 P35/SI2 P36/PTO1 P37/PTO2 VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC P21/HAK P22/HRQ P23/RDY P24/CLK P25/WR P26/RD P27/ALE 5 MB89850R Series (Top view) P43/RT03/W P44/X P45/Y P46/Z P47/TRGI P30/SCKI P31/SOI VCC P32/SI1 P33/SCK2 P34/SO2 P35/SI2 P36/PTO1 P42/RTO2/V P41/RTO1/U P40/RTO0 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P64/DTTI P63/INT3/ADST P62/INT2 P61/INT1 P60/INT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P37/PTO2 VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC 6 RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK (FPT-64P-M06) (FPT-64C-A02) MB89850R Series s PIN DESCRIPTION Pin no. SH-DIP 30 31 28 29 27 *1 QFP 23 24 21 22 20 *2 Pin name X0 X1 MOD0 MOD1 RST Circuit type A B C Function Crystal oscillator pins (10 MHz) Operating mode selection pins Connect directly to VCC or VSS. Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. "L" is output from this pin by an internal reset source. The internal circuit is initialized by the input of "L". General-purpose I/O ports When an external bus is used, these ports function as multiplex pins of lower address output and data I/O. General-purpose I/O ports When an external bus is used, these ports function as upper address output. General-purpose output port When an external bus is used, this port can also be used as a buffer control output. General-purpose output port When an external bus is used, this port can also be used as a hold acknowledge output. General-purpose output port When an external bus is used, this port can also be used as a hold request input. General-purpose output port When an external bus is used, this port functions as a ready input. General-purpose output port When an external bus is used, this port functions as a clock output. General-purpose output port When an external bus is used, this port functions as a write signal output. General-purpose output port When an external bus is used, this port functions as a read signal output. General-purpose output port When an external bus is used, this port functions as an address latch signal output. General-purpose I/O port Also serves as the clock I/O for the UART. This port is a hysteresis input type. 56 to 49 49 to 42 P00/AD0 to P07/AD7 P10/A08 to P17/A15 P20/BUFC D 48 to 41 41 to 34 D 40 33 F 39 32 P21/HAK F 38 31 P22/HRQ D 37 30 P23/RDY D 36 29 P24/CLK F 35 28 P25/WR F 34 27 P26/RD F 33 26 P27/ALE F 2 59 P30/SCK1 E *1: DIP-64P-M01, DIP-64C-A06 *2: FPT-64P-M06, FPT-64C-A02 (Continued) 7 MB89850R Series (Continued) Pin no. SH-DIP*1 1 QFP*2 58 Pin name P31/SO1 Circuit type E Function General-purpose I/O port Also serves as the data output for the UART. This port is a hysteresis input type. General-purpose I/O port Also serves as the data input for the UART. This port is a hysteresis input type. General-purpose I/O port Also serves as the clock I/O for the 8-bit serial I/O. This port is a hysteresis input type. General-purpose I/O port Also serves as the data output for the 8-bit serial I/O. This port is a hysteresis input type. General-purpose I/O port Also serves as the data input for the 8-bit serial I/O. This port is a hysteresis input type. General-purpose I/O port Also serves as the pulse output for the 8-bit PWM timer 1. This port is a hysteresis input type. General-purpose I/O port Also serves as the pulse output for the 8-bit PWM timer 2. This port is a hysteresis input type. General-purpose I/O port Also serves as the pulse output for the timer unit. This port is a hystereisis input type. General-purpose I/O ports Also serve as the pulse output or non-overlap threephase waveform output for the timer unit. These ports are a hysteresis input type. General-purpose I/O ports Also serve as a non-overlap three-phase waveform output. These ports are a hysteresis input type. General-purpose I/O port Also serves as the trigger input for the timer unit. This port is a hysteresis input type. N-ch open-drain output ports Also serve as the analog input for the A/D converter. General-purpose input ports Also serve as an external interrupt input. These ports are a hysteresis input type. General-purpose input port Also serves as an external interrupt input and as the activation trigger input for the A/D converter. This port is a hysteresis input type. 63 56 P32/SI1 E 62 55 P33/SCK2 E 61 54 P34/SO2 E 60 53 P35/SI2 E 59 52 P36/PTO1 E 58 51 P37/PTO2 E 10 3 P40/RTO0 E 9, 8, 7 6, 5, 4 3 2, 1, 64 63, 62, 61 60 P41/RTO1/U, P42/RTO2/V, P43/RTO3/W P44/X, P45/Y, P46/Z P47/TRGI E E E 11 to 18 26 to 24 4 to 11 19 to 17 P50/AN0 to P57/AN7 P60/INT0 to P62/INT2 P63/INT3/ ADST G H 23 16 H *1: DIP-64P-M01, DIP-64C-A06 *2: FPT-64P-M06, FPT-64C-A02 8 (Continued) MB89850R Series (Continued) Pin no. SH-DIP*1 22 QFP*2 15 Pin name P64/DTTI Circuit type H Function General-purpose input port Also serves as a dead-time timer disable input. This port is a hysteresis input type. DTTI input is with a noise canceller. Power supply pin Power supply (GND) pins A/D converter power supply pin A/D converter reference voltage input pin A/D converter power supply (GND) pin Use this pin at the same voltage as VSS. 64 32, 57 19 20 21 57 25, 50 12 13 14 VCC VSS AVCC AVR AVSS -- -- -- -- -- *1: DIP-64P-M01, DIP-64C-A06 *2: FPT-64P-M06, FPT-64C-A02 9 MB89850R Series s I/O CIRCUIT TYPE Type A X1 Circuit Remarks * At an oscillation feedback resistor of approximately 1 M/5.0 V X0 Standby control signal B C R P-ch * At an output pull-up resistor (P-ch) of approximately 50 k/5.0 V * Hysteresis input N-ch D R P-ch P-ch * * * * CMOS output CMOS input Pull-up resistor optional (Mask ROM products) At a pull-up resistor of approximately 50 k/5.0 V N-ch E R P-ch P-ch * * * * CMOS output Hysteresis input Pull-up resistor optional (Mask ROM products) At a pull-up resistor of approximately 50 k/5.0 V N-ch (Continued) 10 MB89850R Series (Continued) Type F R P-ch P-ch Circuit Remarks * CMOS output * Pull-up resistor optional (Mask ROM products) * At a pull-up resistor of approximately 50 k/5.0 V N-ch G N-ch Analog input * N-ch open-drain output * Analog input H R * Hysteresis input * Pull-up resistor optional (Mask ROM products) * At a pull-up resistor of approximately 50 k/5.0 V 11 MB89850R Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pin Be sure to leave (internally connected) N.C. pin open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 12 MB89850R Series s PROGRAMMING TO THE EPROM ON THE MB89P857/W857 The MB89P857/W857 are an OTPROM version of the MB89850R series. 1. Features * 32-Kbyte PROM on chip * Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below. Address 0000H Single chip EPROM mode ( Corresponding addresses on the EPROM programmer) I/O 0080H RAM 0480H Not available 8000H 0000H PROM 32 KB EPROM 32 KB FFFFH 7FFFH 3. Programming to the EPROM In EPROM mode, the MB89P857/W857 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. * Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH (note that addresses 8000H to FFFFH while operating as a single chip assign to addresses 0000H to 7FFFH in EPROM mode.) (3) Program to 0000H to 7FFFH with the EPROM programmer. 13 MB89850R Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150C, 48 Hrs. Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. Erasure In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (A)) with intensity of 12000 W/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the internal EPROM and similar devices, will erase with light sources having wavelengths shorter than 4000 A. Although erasure time will be much longer than with UV source at 2537 A, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package windows should be covered by an opaque label or substance. 7. EPROM Programmer Socket Adapter Package DIP-64P-M01 FPT-64P-M06 FPT-64P-A02 Compatible socket adapter ROM-64SD-28DP-8L* ROM-64QF-28DP-8L ROM-64QF-28DP-8L5 * : Connect the adapter jumper pin to VSS when using. Inquiry: Sun Hayato Co., Ltd.: Fax 81-3-5396-9106 14 MB89850R Series s BLOCK DIAGRAM X0 X1 Oscillator Timebase timer Clock controller 8-bit PWM timer 2 P37/PTO2 RST Reset circuit (WDT) 8-bit PWM timer 1 P36/PTO1 8-bit serial I/O Ports 0 and 1 CMOS I/O port Internal bus 8 P35/SI2 P34/SO2 P33/SCK2 P32/SI1 P31/SO1 P30/SCK1 P00/AD0 to P07/AD7 P10/A08 to P17/A15 MOD0 MOD1 P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC UART 8 External bus interface CMOS I/O port CMOS I/O port Port 2 Port 4 Port 3 6 Timer unit CMOS output port (Dead-time timer) P47/TRGI P46/Z P45/Y P44/X P43/RTO3/W P42/RTO2/V P41/RTO1/U P40/RTO0 P64/DTTI 4 External interrupt 3 P60/INT0 to P62/INT2 P63/INT3/ADST Input port AVR AVCC AVSS Port 5 8 10-bit A/D converter 8 P50/AN0 to P57/AN7 RAM F2MC-8L CPU ROM Other pins VCC , VSS x 2 Part number MB89855R MB89W857/P857 RAM size 512 bytes 1 Kbyte ROM size 16 Kbytes 32 Kbytes (EPROM) N-ch open-drain output port Port 6 15 MB89850R Series s CPU CORE 1. Memory Space The microcontrollers of the MB89850R series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89860/850 series is structured as illustrated below. * Memory Space MB89W857/P857 MB89855R 0000H I/O 0080H RAM 512 B 0100H Register 0200H 0280H 0000H I/O 0080H RAM 1 KB 0100H Register 0200H 0480H External area External area 8000H C000H ROM* 32 KB ROM* 16 KB FFFFH FFFF H *: The ROM area is an external area depending on the mode. 16 MB89850R Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code Initial value : Program counter : Accumulator FFFDH Indeterminate 16 bits PC A T IX EP SP PS : Temporary accumulator Indeterminate : Index register : Extra pointer : Stack pointer : Program status Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 Other bits are indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) * Structure of the Program Status Register 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 17 MB89850R Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. * Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes b1 b0 "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 18 MB89850R Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89850R series. The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. * Register Bank Configuration This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 19 MB89850R Series s I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H to 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H (R/W) (W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) CTR1 CMR1 CTR2 CMR2 SMC SRC SSD SIDR/SODR SMR SDR (R/W) PDR8 (R/W) PDR7 (R) PDR6 (R/W) (W) (R/W) (W) (R/W) PDR3 DDR3 PDR4 DDR4 PDR5 (R/W) (W) (R/W) STBC WDTC TBTC Read/write (R/W) (W) (R/W) (W) (R/W) (W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 BCTR Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register External bus pin control register Vacancy Vacancy Standby control register Watchdog timer control register Timebase timer control register Vacancy Port 3 data register Port 3 data direction register Port 4 data register Port 4 data direction register Port 5 data register Vacancy Port 6 data register Vacancy Port 7 data register Vacancy Port 8 data register Vacancy PWM control register 1 PWM compare register 1 PWM control register 2 PWM compare register 2 UART serial mode control register UART serial rate control register UART serial status/data register UART serial data register Serial mode register Serial data register (Continued) 20 MB89850R Series (Continued) Address 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H to 7BH 7CH 7DH 7EH 7FH (W) (W) (W) ILR1 ILR2 ILR3 (W) (W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (W) (W) (W) (W) (W) (W) (W) (W) ZOCTR CLRBRH CLRBRL TCSR CICR TMCR COER CMCR DTCR DTSR OCTBR OCPBR0H OCPBR0L OCPBR1H OCPBR1L OCPBR2H OCPBR2L OCPBR3H OCPBR3L Read/write (R/W) (R/W) (R/W) (R/W) (R) (R) Register name EIC1 EIC2 ADC1 ADC2 ADDH ADDL Register description External interrupt control register 1 External interrupt control register 2 A/D converter control register 1 A/D converter control register 2 A/D converter data register (H) A/D converter data register (L) Vacancy Zero detection output control register Compare clear buffer register (H) Compare clear buffer register (L) Timer control status register Compare interrupt control register Timer mode control register Compare/port selection register Compare buffer mode control register Dead-time timer control register Dead-time setting register Output control buffer register Output compare buffer register 0 (H) Output compare buffer register 0 (L) Output compare buffer register 1 (H) Output compare buffer register 1 (L) Output compare buffer register 2 (H) Output compare buffer register 2 (L) Output compare buffer register 3 (H) Output compare buffer register 3 (L) Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy Notes: * Do not use vacancies. * When a read-modify-write instruction (such as bit set) is used to access a write-only register or a register containing a write-only bit, a bit designated by the instruction will have a predetermined value. However, a write-only bit included, if any, in bits not defined by the instruction will cause a malfunction. So no access to the register should be tried with any read-modefy-write instruction. 21 MB89850R Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Power supply voltage Symbol VCC AVCC Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -- -- -40 -55 Max. VSS + 7.0 VSS + 7.0 13.0 VCC + 0.3 VSS + 0.3 20 4 15 30 50 -20 -4 -20 300 +85 +150 Unit V V V V V mA mA mA mA mA mA mA mA mW C C P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57 P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57 P40 to P47 * AVR must not exceed AVCC + 0.3 V. MOD1 pins of MB89P857/ W857 Remarks A/D converter reference input voltage AVR Program voltage Input voltage Output voltage "L" level maximum output current VPP VI VO IOL IOLAV1 IOLAV2 IOLAV1 IOLAV2 "H" level maximum output current "H" level average output current "H" level total maximum output current Power consumption Operating temperature Storage temperature IOH IOHAV IOH PD TA Tstg "L" level average output current "L" level total average output current *: Use AVCC and VCC set at the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. WARNING: Permanent device damage may occur if the above "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 22 MB89850R Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol Value Min. 2.7* Power supply voltage VCC AVCC 2.7* 1.5 A/D converter reference input voltage Operating temperature AVR TA 0.0 -40 Max. 6.0* 5.5* 6.0 AVCC +85 Unit V V V V C Remarks Normal operation assurance range* MB89855R Normal operation assurance range* MB89P857/W855 Retains the RAM state in stop mode *: These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1 and "5. A/D Converter Electrical Characteristics." Note: Connect the MOD0 and MOD1 pins to VCC or VSS. 6 5.5 5 Operation assurance range Operating voltage (V) 4 Analog accuracy assured in the VCC = AVCC = 3.5 V to 6.0 V range 3 2 1 1 2 3 4 5 6 7 8 9 10 Clock operating frequency (MHz) (s) 4.0 2.0 0.8 0.4 Minimum execution time (instruction cycle) Note: The shaded area is assured only for the MB89855R. Figure 1 Operating Voltage vs. Clock Operating Frequency 23 MB89850R Series 3. DC Characteristics (AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol VIH "H" level input voltage Pin name P00 to P07, P10 to P17, P22, P23 RST, P30 to P37, P40 to P47, P60 to P64 P00 to P07, P10 to P17, P22, P23 RST, P30 to P37, P40 to P47, P60 to P64 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P57 P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P64, MOD0, MOD1 RST Condition -- -- -- -- Value Min. 0.7 VCC Typ. -- -- -- -- Max. VCC + 0.3 Unit V V V V Remarks VIHS VIL "L" level input voltage 0.8 VCC VCC + 0.3 VSS - 0.3 0.3 VCC VILS VSS - 0.3 0.2 VCC "H" level output voltage VOH IOH = -2.0 mA 2.4 -- -- V "L" level output voltage VOL IOL = +1.8 mA -- -- 0.4 V VOL2 IOL = +1.5 mA -- -- 1.5 V Input leackage current ILI1 0.0 V < VI < VCC -- -- 5 A Pull-up resistance RPULL ICC VI = 0.0 V FC = 10 MHz Normal operation mode (External clock) 25 -- 50 15 100 18 k mA With pull-up resistor ICCS Power supply current VCC FC = 10 MHz Sleep mode (External clock) Stop mode TA = +25C -- -- 6 -- 8 10 mA A A pF ICCH IA CIN AVCC Other than AVCC, AVSS, VCC, and VSS FC = 10 MHz, when A/D conversion is activated f = 1 MHz -- -- 6 10 -- -- Input capacitance 24 MB89850R Series 4. AC Characteristics (1) Reset Timing (VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Parameter RST "L" pulse width Symbol tZLZH Condition Min. -- 16 tXCYL* Max. -- ns Unit Remarks * : tXCYL is the oscillation cycle (1/FC) to input to the X0 pin. t ZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Parameter Power supply rising time Power supply cut-off time Symbol tR -- tOFF 1 -- ms Due to repeated operations Condition Min. -- Max. 50 ms Power-on reset function only Unit Remarks Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR 2.0 V 0.2 V 0.2 V tOFF VCC 0.2 V 25 MB89850R Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol FC tXCYL PWH PWL tCR tCF Pin name X0, X1 -- X0 -- 10 ns External clock Condition Value Min. 1 100 20 Max. 10 1000 -- Unit MHz ns ns External clock Remarks * X0 and X1 Timing Conditions tXCYL PWH tCR 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tCF PWL X0 0.2 VCC * Clock Conditions When a crystal or ceramic resonator is used When an external clock is used X0 X1 X0 X1 Open (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol tinst Value (typical) 4/FC Unit s Remarks tinst = 0.4 s when operating at FC = 10 MHz 26 MB89850R Series (5) Clock Output Timing (VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Cycle time CLK CLK Symbol tCYC CLK tCHCL Pin name Condition Load condition: 50 pF Value Min. 200 30 Max. -- 100 Unit ns ns Remarks tXCYL x 2 at 10 MHz oscillation Approx. tCYC/2 at 10 MHz oscillation t CYC t CHCL 2.4 V 2.4 V 0.8 V CLK 27 MB89850R Series (6) Bus Read Timing (VCC = +5.0 V10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Valid address RD time RD pulse width Valid address data read time RD data read time RD data hold time RD ALE time RD address invalid time Symbol tAVRL tRLRH tAVDV tRLDV tRHDX tRHLH tRHAX tRLCH tCLRH tRLBL tBHAV Pin name RD, A15 to A08, AD7 to AD0 Condition Value (10 MHz) Min. 1/4 tinst * - 64 ns 1/2 tinst * - 20 ns Max. -- -- 1/2 tinst* 1/2 tinst * - 80 ns Unit Remarks ns ns ns ns ns ns ns ns ns ns ns No wait No wait RD AD7 to AD0, A15 to A08 RD, AD7 to AD0 AD7 to AD0, RD -- -- Load condition: 50 pF 0 1/4 tinst * - 40 ns 1/4 tinst * - 40 ns 1/4 tinst * - 60 ns -- -- -- -- -- -- -- RD, ALE RD, A15 to A08 RD CLK time CLK RD time RD BUFC time BUFC valid address time RD, CLK RD, BUFC A15 to A08, AD7 to AD0, BUFC 0 -5 5 * : For information on tinst, see "(4) Instruction Cycle." CLK 2.4 V 0.8 V tRHLH ALE 0.8 V AD 2.4 V 0.8 V tAVDV 0.7 VCC 0.3 VCC 0.7 VCC 0.3 VCC tRHDX 2.4 V 0.8 V A 2.4 V tRLCH 0.8 V tAVRL tRLDV tRLRH 2.4 V tCLRH 0.8 V tRHAX 2.4 V 0.8 V RD 0.8 V tRLBL 2.4 V tBHAV 2.4 V BUFC 0.8 V 28 MB89850R Series (7) Bus Write Timing (VCC = +5.0 V10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Valid address ALE time ALE time address invalid time Valid address WR time Symbol tAVLL tLLAX tAVWL tWLWH tDVWH tWHDX tWHLH tWLCH tCLWH tLHLL tLLCH Pin name Condition Value (10 MHz) Min. 1/4 tinst *1 - 64 ns Max. -- -- -- -- -- -- -- -- -- -- *2 Unit Remarks ns ns ns ns ns ns ns ns ns ns ns ns AD7 to AD0, ALE, A15 to A08 5 1/4 tinst *1 - 60 ns 1/2 tinst * - 20 ns 1/2 tinst *1 - 60 ns 1/4 tinst *1 - 40 ns 1/4 tinst * - 40 ns 1/4 tinst * - 40 ns 1/4 tinst *1 - 60 ns 1 1 1 WR, ALE WR AD7 to AD0, WR WR pulse width Write data WR time WR data hold time WR ALE time WR CLK time CLK WR time ALE pulse width ALE CLK time WR address invalid time tWHAX Load WR, A15 to A08 condition: AD7 to AD0, WR 50 pF WR, ALE WR, CLK ALE ALE, CLK 0 tXCYL - 35 ns -- -- tXCYL - 35 ns*2 *1: For information on tinst, see "(4) Instruction Cycle." *2: These characteristics are also applicable to the bus read timing. CLK tLHLL tLLCH 2.4 V 0.8 V ALE 2.4 V 0.8 V tAVLL tLLAX 2.4 V 0.8 V tDVWH 2.4 V 0.8 V tAVWL tWLWH t WHLH 0.8 V AD 2.4 V 2.4 V 0.8 V 0.8 V 2.4 V 0.8 V tWHDX 2.4 V tCLWH 0.8 V tWHAX A tWLCH WR 0.8 V 2.4 V 29 MB89850R Series (8) Ready Input Timing (VCC = +5.0 V10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Parameter RDY valid CLK time CLK RDY invalid time Symbol tYVCH tCHYX Pin name Condition Min. RDY, CLK Load condition: 50 pF 60 0 Max. -- -- ns ns * * Unit Remarks * : These characteristics are also applicable to the read cycle. CLK 2.4 V 2.4 V ALE AD Address Data A WR t YVCH t CHYX 0.7 VCC RDY 0.3 VCC 0.3 VCC t YVCH t CHYX 0.7 VCC Note: The bus cycle is also extended in the read cycle in the same manner. 30 MB89850R Series (9) UART and Serial I/O Timing (VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Serial clock cycle time SCK1 SO1 time SCK2 SO2 time Valid SI1 SCK1 Valid SI2 SCK2 SCK1 valid SI1 hold time SCK2 valid SI2 hold time Serial clock "H" pulse width Serial clock "L" pulse width Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK1,SCK2 Condition Value Min. 2 tinst* -200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* 0 1/2 tinst* 1/2 tinst* Max. -- 200 -- -- -- -- 200 -- -- Unit s ns s s s s ns s s Remarks SCK1, SO1 Internal shift SCK2, SO2 clock mode SI1, SCK1 Load SI2, SCK2 condition: 50 pF SCK1, SI1 SCK2, SI2 SCK1, SCK2 External shift SCK1, SO1 clock mode SCK2, SO2 Load SI1, SCK1 condition: SI2, SCK2 50 pF SCK1, SI1 SCK2, SI2 SCK1 SO1 time SCK2 SO2 time Valid SI1 SCK1 Valid SI2 SCK2 SCK1 valid SI1 hold time SCK2 valid SI2 hold time * : For information on tinst, see "(4) Instruction Cycle." 31 MB89850R Series * Internal Shift Clock Mode tSCYC SCK1 SCK2 0.8 V 2.4 V 0.8 V tSLOV SO1 SO2 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC SI1 SI2 0.8 VCC 0.2 VCC * External Shift Clock Mode t SLSH t SHSL SCK1 SCK2 0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC t SLOV SO1 SO2 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC SI1 SI2 0.8 VCC 0.2 VCC 32 MB89850R Series (10) Peripheral Input Timing (VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Parameter Peripheral input "H" pulse width 1 Peripheral input "L" pulse width 1 Symbol Pin name Condition Min. tILIH1 tIHIL1 TRGI, DTTI, ADST, INT0 to INT3 Load condition: 50 pF 2 tinst* 2 tinst* Max. -- -- s s Unit Remarks * : For information on tinst, see "(4) Instruction Cycle." TRGI DTTI ADST INT0 to INT3 0.2 VCC tIHIL1 tILIH1 0.8 VCC 0.2 VCC 0.8 VCC 5. A/D Converter Electrical Characteristics (AVCC = VCC = +3.5 V to +6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Resolution Linearity error Differential linearity error Total error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time Analog port input current Analog input voltage Reference voltage Reference voltage supply current Symbol Pin name Condition Value Min. -- -- -- Typ. -- -- -- -- Max. 10 2.0 1.5 3.0 Unit Remark s bit LSB LSB LSB -- AVCC = VCC VOT VFST -- IAIN -- IR AVR AN0 to AN7 -- AN0 to AN7 -- AVSS - 1.5 AVSS + 0.5 AVSS + 2.5 LSB AVR - 3.5 AVR - 1.5 AVR + 0.5 LSB -- -- -- -- -- AVR = 5.0 V -- 33 tinst* -- -- -- 200 4 -- 10 AVR AVCC -- LSB s A V V A -- -- 0 0 -- * : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics." 33 MB89850R Series 6. A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter * Linearity error The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1111" "11 1111 1110") from actual conversion characteristics * Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error The total error indicates the difference between the actual value and theoretical value. This error is caused by the zero transition error, full-scale transition error, linearity error, quantization, and noise. Theoretical I/O value 3FF 3FE 3FD Digital output 1.5 LSB Digital output VFST 3FF 3FE 3FD Total error Actual conversion value (1 LSB x N + 0.5 LSB) 004 003 002 001 0.5 LSB AVSS Analog input AVR 004 VNT 003 Actual conversion value Theoretical value 001 VOT 1 LSB 002 AVSS Analog input AVR 1 LSB = VFST - VOT 1022 (V) Total error of digital output "N" = VNT - (1 LSB x N + 0.5 LSB) 1 LSB (Continued) 34 MB89850R Series (Continued) Zero transition error 004 Actual conversion value 003 Digital output Digital output 3FE 3FF Full-scale transition error Theoretical value Actual conversion value 002 Actual conversion value 001 VFST (Measured value) 3FD Actual conversion value 3FC VOT (Measured value) AVSS Analog input Analog input AVR Linearity error 3FF 3FE 3FD Digital output Digital output VFST (Measured VNT value) 004 003 002 Theoretical value 001 VOT (Measured value) AVSS Analog input AVR N-2 Actual conversion value N Actual conversion value (1 LSB x N + VOT) N+1 Differential linearity error Theoretical value Actual conversion value V(N + 1)T N-1 VNT Actual conversion value Analog input Linearity error of digital output "N" = VNT - (1 LSB x N + VOT) 1 LSB Differential linearity error of digital output "N" = V(N + 1)T - VNT 1 LSB -1 35 MB89850R Series 7. Notes on Using A/D Converter * Input impedance of the analog input pins The A/D converter used for the MB89860/850 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for fifteen instruction cycles after activation A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k). Note that if the impedance connot be kept low, it is recommended to connect an external capacitor of about 0.1 F for the analog input pin. * Analog Input Equivalent Circuit Sample hold circuit . C =. 64 pF Anlog input pin Comparator If the analog input impedance is higher than 10 k, it is recommended to connect an external capacitor of approx. 0.1 F. . R = 3 k . Close for 15 instruction cycles after activating A/D conversion. Analog channel selector * Error The smaller the | AVR - AVSS |, the greater the error would become relatively. 36 MB89850R Series s EXAMPLE CHARACTERISTICS (1) "L" Level Output Voltage (P00 to P07, P10 to P17, P20 to P27, P30 to P37, and P50 to P57) (2) "L" Level Output Voltage (P40 to P47) VOL vs. IOL VOL (V) 0.5 VCC = 5.0 V 0.4 0.3 0.2 0.1 VCC = 6.0 V VCC = 3.0 V TA = +25C VCC = 4.0 V VOL (mV) 600 VOL vs. IOL TA = +25C 500 400 VCC = 4.0 V 300 200 100 VCC = 5.0 V VCC = 6.0 V VCC = 3.0 V 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) 0 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 IOL (mA) (3) "H" Level Output Voltage (P00 to P07, P10 to P17, P20 to P27, P30 to P37, and P40 to P47) (4) Pull-up Resistance VCC - VOH (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 -0.5 VCC - VOH vs. IOH TA = +25C VCC = 2.5 V RPULL (k) 1000 RPULL vs. VCC TA = +25C VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 100 -1.0 -1.5 -2.0 -2.5 -3.0 IOH (mA) 10 1 2 3 4 5 6 VCC (V) 37 MB89850R Series (5) "H" Level Input Voltage/"L" Level Input Voltage (CMOS Input) (6) "H" Level Input Voltage/"L" level Input Voltage (Hysteresis Input) VIN vs. VCC VIN vs. VCC VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 4 5 6 7 VCC (V) TA = +25C VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 4 5 6 7 VCC (V) VILS VIHS TA = +25C VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level (7) Operating Supply Current vs. Frequency (8) Operating Supply Current vs. VCC ICC vs. FC ICC (mA) 10 TA = +25C 8 VCC = 5.0 V 20 ICC (mA) 25 ICC vs. VCC TA = +25C 6 15 VCC = 3.5 V VCC = 3.0 V FC = 10 MHz FC = 8 MHz FC = 6 MHz FC = 4 MHz 4 10 2 5 0 2 4 6 8 10 FC (MHz) 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VCC (V) 38 MB89850R Series (9) Sleep Power Supply Current vs. Frequency (10) Sleep Power Supply Current vs. VCC ICCS vs. FC ICCS (mA) 10 TA = +25C 8 8 ICCS (mA) 10 ICCS vs. VCC TA = +25C 6 VCC = 5.0 V 4 VCC = 3.5 V 2 VCC = 3.0 V 6 FC = 10 MHz FC = 8 MHz FC = 6 MHz 4 FC = 4 MHz 2 0 2 4 6 8 10 FC (MHz) 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VCC (V) 39 MB89850R Series s INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups: * Transfer * Arithmetic operation * Branch * Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri x (x) (( x )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH prior to the instruction executed. * 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F. 40 MB89850R Series Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC Note ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 During byte transfer to A, T A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 41 MB89850R Series Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA C A (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (Continued) 42 MB89850R Series (Continued) Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 Table 4 TL - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - - NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5 Other Instructions (9 instructions) Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ 4 4 4 4 1 1 1 1 1 # 1 1 1 1 1 1 1 1 1 43 44 3 RETI PUSHW POPW MOV MOVW CLRI A A A,ext A,PS SETC SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP ,A A,SP SUBC A A A, T A A A XCH XOR AND OR H L 0 1 2 0 NOP SWAP RET 1 MULU DIVU A A JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A 2 ROLC CMP ADDC s INSTRUCTION MAP A A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX 3 RORC CMPW A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS A ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP ,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC MB89850R Series 4 MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 5 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP ,#d16 A,SP 6 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX 7 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP ,A A,@EP A,@EP A,@EP @EP ,#d8 @EP ,#d8 dir: 7 dir: 7,rel A,@EP @EP ,A EP ,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 R5 R4 R3 R2 R1 R0 CALLV BNC #0 rel CALLV BC #1 CALLV BP #2 CALLV BN #3 8 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel 9 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel rel A MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel rel B MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel rel CALLV BNZ #4 rel CALLV BZ #5 C MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel rel CALLV BGE #6 rel CALLV BLT #7 E MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel rel MB89850R Series s MASK OPTIONS (MB89855R) Option type Power-on reset Initial value of oscillation stabilization delay time Reset pin output Pull-up resistor at port pin P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P64 Option selection 0: Without power-on reset 1: With power-on reset 0: 218/FC (s) (Crystal oscillator) 1: 214/FC (s) (Ceramic oscillator) 0: Without reset output 1: With reset output 1: Without pull-up resistor 0: With pull-up resistor Remarks -- Selects the initial value of the OSCS bit in the STBC register during power-on reset. -- * Can be set per pin. * P00 to P07, P10 to P17, and P20 to P27 with a pull-up resistor can be set only for single-chip mode. s STANDARD OPTION LIST Part number Parameter Power-on reset Initial value of oscillation stabilization delay time Output at reset pin Pull-up resistor at port pin MB89P857/W857 Available 218/FC (s) Available Not available s ORDERING INFORMATION Part number MB89855RP-SH MB89P857P-SH MB89W857C-SH MB89W857CF-ES-BND Package 64-pin Plastic SH-DIP (DIP-64P-M01) 64-pin Ceramic SH-DIP (DIP-64C-A06) 64-pin Ceramic QFP (FPT-64C-A02) ES level only ES level only Remarks 45 MB89850R Series s PACKAGE DIMENSIONS 64-pin Plastic SH-DIP (DIP-64P-M01) 58.00 -0.55 +.008 2.283 -.022 +0.22 INDEX-1 INDEX-2 17.000.25 (.669.010) 5.65(.222)MAX 3.00(.118)MIN 1.00 -0 +.020 .039 -0 1.7780.18 (.070.007) 1.778(.070) MAX 55.118(2.170)REF +0.50 0.250.05 (.010.002) 0.450.10 (.018.004) 0.51(.020)MIN 15MAX 19.05(.750) TYP C 1994 FUJITSU LIMITED D64001S-3C-4 Dimensions in mm (inches) 64-pin Ceramic SH-DIP (DIP-64C-A06) 56.900.56 (2.240.022) R1.27(.050) REF 8.89(.350) DIA TYP 18.750.25 (.738.010) INDEX AREA 1.270.25 (.050.010) 5.84(.230)MAX 0.250.05 (.010.004) 3.400.36 (.134.014) 1.7780.180 (.070.007) 0.900.10 (.0355.0040) 55.118(2.170)REF 0.46 -0.08 +.005 .018 -.003 +0.13 19.050.25 (.750.010) 0~9 1.45(.057) MAX C 1994 FUJITSU LIMITED D64006SC-1-2 Dimensions in mm (inches) 46 MB89850R Series 64-pin Plastic QFP (FPT-64P-M06) 51 24.700.40(.972.016) 20.000.20(.787.008) 33 3.35(.132)MAX 0.05(.002)MIN (STAND OFF) 52 32 14.000.20 (.551.008) INDEX 64 20 18.700.40 (.736.016) 12.00(.472) REF 16.300.40 (.642.016) "A" LEAD No. 1 19 1.00(.0394) TYP 0.400.10 (.016.004) 0.150.05(.006.002) 0.20(.008) M Details of "A" part 0.25(.010) "B" 0.10(.004) 18.00(.709)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX Details of "B" part 0 10 1.200.20 (.047.008) C 1994 FUJITSU LIMITED F64013S-3C-2 Dimensions in mm (inches) 64-pin Ceramic QFP (FPT-64C-A02) 0.51(.020) TYP 9.40(.370)TYP 12.01(.473) REF 17.91(.705) TYP 16.00(.630) 14.000.25 TYP (.551.010) 16.31(.642) TYP INDEX AREA 1.000.10 0.400.08 (.0394.0040) (.016.003) 18.00(.709) REF 20.000.25 (.787.010) 23.90(.941) TYP 22.00(.866) TYP 1.000.10 (.0394.0040) 0.150.05 (.006.002) 1.60(.063) TYP 4.70(.185)MAX 22.30(.878) TYP 0.80(.0315) TYP C 1994 FUJITSU LIMITED F64012SC-2-2 Dimensions in mm (inches) 47 MB89850R Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F9609 (c) FUJITSU LIMITED Printed in Japan |
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